Japanese Patent Application No. 2001-21931, filed on Jan. 30, 2001, is hereby incorporated by reference in its entirety.
1. Technical Field
The present invention relates to a method of manufacturing a semiconductor integrated circuit device including nonvolatile semiconductor memory devices.
2. Related Art
As one type of nonvolatile semiconductor memory device, a MONOS (Metal Oxide Nitride oxide Semiconductor) memory device is known. In the MONOS memory device, a gate insulating layer disposed between a channel and a gate is formed of a laminate consisting of two silicon oxide layers and a silicon nitride layer, and charges are trapped in the silicon nitride layer.
A device shown in FIG. 16 is known as such a MONOS nonvolatile semiconductor memory device (Y. Hayashi, et al., 2000 Symposium on VLSI Technology Digest of Technical Papers, 122-123).
In this MONOS memory cell 100, a word gate 14 is formed on a semiconductor substrate 10 with a first gate insulating layer 12 interposed. A first control gate 20 and a second control gate 30 are disposed on either side of the word gate 14 in the shape of sidewalls. A second gate insulating layer 22 is present between the bottom of the first control gate 20 and the semiconductor substrate 10. A side insulating layer 24 is present between the side of the first control gate 20 and the word gate 14. A second gate insulating layer 32 is present between the bottom of the second control gate 30 and the semiconductor substrate 10. A side insulating layer 34 is present between the side of the second control gate 30 and the word gate 14. Impurity diffusion layers 16 and 18 forming a source region or a drain region are formed in the semiconductor substrate 10 in a region between the control gate 20 and the control gate 30 facing each other in adjacent memory cells.
As described above, one memory cell 100 includes two MONOS memory elements, one on each side of the word gate 14. These MONOS memory elements can be controlled separately. Therefore, the memory cell 100 is capable of storing 2 bits of information.
This MONOS memory cell operates as follows. One of the control gates of the memory cell 100 is capable of selecting read or write operation separately by biasing the other control gate to an override voltage.
A write (program) operation is described below with reference to a case where electrons are injected into the second gate insulating layer (ONO film) 32 at the left in CG [i+1] in FIG. 16. In this case, the bit line (impurity diffusion layer) 18 (D[i+1]) is biased to a drain voltage of 4 to 5 V. The control gate 30 (CG[i+1]) is biased to 5 to 7 V in order to cause hot electrons to be injected into the second gate insulating layer 32 at the left of the control gate 30 (CG[i+1]). A word line connected to the word gates 14 (Gw[i] and Gw[i+1]) is biased at a voltage slightly higher than the threshold value of the word gate in order to limit the program current to a specific value (10 xcexcA or less). The control gate 20 (CG[i]) is biased to an override voltage. This override voltage enables a channel under the control gate 20 (CG[i]) to conduct irrespective of the memory state. A left side bit line 16 (D[i]) is biased to ground. Control gates and diffusion layers in unselected memory cells are grounded.
In an erase operation, stored charges (electrons) are erased by injection of hot holes. Hot holes can be generated by Bxe2x80x94B tunneling at the surface of the bit diffusion layer 18. At this time, the voltage Vcg of the control gate is biased to a negative voltage (xe2x88x925 to xe2x88x926 V) and the voltage of the bit diffusion layer is biased to 5 to 6 V.
In the above-cited reference, according to the MONOS memory cell, two separately controllable programming sites in a single memory cell can provide bit density of 3F2.
According to one embodiment of the present invention, there is provided a method of manufacturing a semiconductor integrated circuit device including a memory cell array in which nonvolatile semiconductor memory devices are arranged in a matrix of a plurality of rows and columns, the method comprising the following steps (a) to (k):
(a) a step of forming an element isolation region on the surface of a semiconductor layer;
(b) a step of forming a first gate insulating layer and a laminate having a first conductive layer for a word gate disposed over the first gate insulating layer on the semiconductor layer, the laminate having a plurality of openings extending in a first direction;
(c) a step of forming second gate insulating layers on the semiconductor layer so as to be adjacent to both sides of the first gate insulating layer;
(d) a step of forming side insulating layers on both sides of the first conductive layer for the word gate;
(e) a step of forming a second conductive layer over the entire surface of a structure formed by the steps (a) to (d) so as to cover the structure;
(f) a step of forming a first mask layer on the second conductive layer at least in a region in which a common contact section is formed;
(g) a step of forming a control gate and a common contact section which comprises:
anisotropically etching the entire surface of the second conductive layer to form first and second control gates in the shape of sidewalls continuous in the first direction on either side of the side insulating layers, and to form a contact conductive layer at least in a region in which the common contact section is formed; and
forming the contact conductive layer continuously with a pair of the first and second control gates adjacent in a second direction which intersects the first direction;
(h) a step of doping the semiconductor layer located between the first and second control gates with impurities, and forming an impurity diffusion layer which forms a source region or a drain region;
(i) a step of forming an insulating layer which covers the first and second control gates;
(j) a step of forming a second mask layer in a region in which the common contact section is formed; and
(k) a step of patterning the first conductive layer for the word gate.
According to this method of manufacturing a semiconductor integrated circuit device, the common contact section can be formed together with the control gate in the shape of sidewall without increasing the number of steps. The size and shape of the common contact section can be specified by the first and second mask layers at the time of patterning, whereby a sufficient contact area can be secured. Therefore, an electrical connection with narrow control gates can be secured reliably through the common contact sections.
According to this a manufacturing method, a semiconductor integrated circuit device including a memory cell array, in which nonvolatile semiconductor memory devices are arranged in a matrix of a plurality of rows and columns, having the following structure can be obtained.
The nonvolatile semiconductor memory device comprises:
a word gate formed on a semiconductor layer with a first gate insulating layer interposed,
an impurity diffusion layer which forms either a source region or a drain region formed in the semiconductor layer, and
first and second control gates in the shape of sidewalls formed along either side of the word gate, wherein:
the first control gate is disposed on the semiconductor layer with a second gate insulating layer interposed and also on the word gate with a side insulating layer interposed,
the second control gate is disposed on the semiconductor layer with a second gate insulating layer interposed and also on the word gate with a side insulating layer interposed,
each of the first and second control gates is disposed continuously in a first direction, and
a pair of the first and second control gates adjacent in a second direction which intersects the first direction is connected to a common contact section.
The manufacture method of the present invention may have the following features.
(A) The second conductive layer for the control gate and the common contact section may be formed of a doped polysilicon layer.
(B) The second gate insulating layer may be formed by depositing a first silicon oxide layer, a silicon nitride layer, and a second silicon oxide layer one after another. The side insulating layer and the insulating layer in the common contact section may be formed during this step.
(C) The step (b) may comprise a step of forming a stopper layer for chemical mechanical polishing (CMP) on the first conductive layer for the word gate, and
in the step (i), the insulating layer which covers the first and second control gates may be provided by forming an insulating layer on the entire surface of the structure formed by the steps (a) to (h) and then removing the insulating layer by chemical mechanical polishing until the stopper layer is exposed. An insulating layer formed in this manner is hereinafter called a xe2x80x9cburied insulating layerxe2x80x9d.
(D) The stopper layer may be formed so that an upper surface thereof is located at a position higher than an upper end of the control gate. In this case, the side insulating layer may be formed so that an upper end thereof is located at the same level as an upper surface of the stopper layer. Therefore, the upper end of the side insulating layer is located at a position higher than the control gate with respect to the semiconductor layer. This prevents current leakage and short circuits between the control gates and interconnect layers for the word gates formed on the control gates with the buried insulating layers interposed.
(E) The common contact sections may be provided adjacent to an end of the impurity diffusion layer. The common contact sections may be provided alternately on one end and the other end of a plurality of the impurity diffusion layers.
(F) The memory cell array may be divided into a plurality of blocks. In this case, contact impurity diffusion layer may be formed in the semiconductor layer after the step (a), and the impurity diffusion layer in one of the blocks may be connected to the impurity diffusion layer in another one of the blocks adjacent to the one block in a first direction through the contact impurity diffusion layer.
(G) The first mask layer may be formed corresponding to a region in which the common contact section is formed in the step (f).
In the step (f), the first mask layer may be formed continuously so as to cover regions in which a plurality of the common contact sections arranged in the second direction are formed. In this case, in the step (g), a conductive layer may be continuously formed so as to include regions in which the common contact sections are formed, by the first mask layer. In the step (k), the contact conductive layer may be formed together with the word gate by patterning the conductive layer together with the first conductive layer.